Senior/Staff Silicon Quality & Reliability Engineer at PowerLattice
PowerLattice is hiring a Senior/Staff Silicon Quality & Reliability Engineer in Chandler, AZ, US +1 more. Remote.
About PowerLattice
PowerLattice is a semiconductor startup developing power delivery chiplets for AI accelerators and GPUs. Its solution moves voltage regulation into the processor package to reduce power loss and heat dissipation, aiming to support higher-power AI chips. The company describes its technology as the industry's first power delivery chiplet and says it is backed by Silicon Valley venture capital firms.
Senior/Staff Silicon Quality & Reliability Engineer job description
Hybrid requiring 3 days a week onsite in the office
Reports To: Head of Engineering
About Us
Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.
About the Role
We are seeking a highly skilled and hands-on Quality and Reliability Engineer to own company-wide quality, reliability, and design-for-reliability (DfR) initiatives. You will bridge the gap between design teams, wafer foundries, and OSAT partners. Your mission is to establish rigorous quality gates, build predictive reliability models, and mitigate risks from development through high-volume manufacturing.
Key Responsibilities
Quality & Vendor Management
Collaborate Cross-Functionally: Partner with foundries, OSATs, and internal teams to define process quality and reliability requirements.
Drive Ecosystem Partners: Manage external suppliers through test vehicle qualifications and manufacturing quality improvements before tape-out.
Monitor Quality Metrics: Oversee supplier quality, manufacturing excursions, and product return evaluations to ensure continuous improvements.
Qualification & Risk Mitigation
Lead Product Qualification: Support internal product bring-ups, qualifications, and the disposition of excursion materials using risk assessments.
Develop Lifecycle Models: Plan and execute stress testing with partners to build predictive models for extrinsic and intrinsic failure mechanisms.
Design & Methodology Strategy
Direct DfR Initiatives: Conduct wear out reliability assessments and guide design teams to optimize next-generation product architectures.
Standardize Quality Systems: Establish company-wide quality guidelines, qualification standards, and advanced frameworks to maximize product lifetime
Preferred Qualifications
Education & Experience
Advanced Degree: PhD or MS in Electrical Engineering, Physics, Materials Science, or a related field.
Proven Track Record: 8+ years of hands-on experience in semiconductor process, quality management, and product reliability.
Technical Expertise
Quality & Reliability Physics: Deep command of semiconductor physics, acceleration models, and wear out mechanisms (TDDB, BTI, HCI, EM, SM).
Industry Standards: Direct experience with wafer-level reliability (WLR) tests, test structures, and quality standards (JEDEC, AEC-Q100, ISO 9001).
Statistical Proficiency: Expert in quality and reliability statistics (e.g., JMP), SPC charting, and failure rate calculations across the bathtub curve.
Failure Analysis: Strong knowledge of semiconductor defects, root-cause failure analysis (FA), 8D problem solving, and defect screening.
Circuit Dynamics: Solid understanding of quality degradation mechanisms in logic, memory, and analog circuits.
Leadership & Soft Skills
Communication: Excellent written, verbal, and presentation skills to interface with executive leadership and external vendors.
Apply now
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