Director, Physical Design at Kepler Computing

Kepler is building a new class of AI memory and logic.

We combine advanced materials, 3D architectures and deep semiconductor expertise to address fundamental physical limits in computing, including the space and energy required to support growing compute demands.

Our team has shipped technologies used in billions of devices and by hundreds of millions of people. We are backed by pioneers in computing and leading semiconductor companies and work alongside major customers and partners to move new technology from the lab toward real-world application.

At Kepler, you’ll work with curious, driven people solving complex technical challenges through experimentation, evidence and iteration. Your work will contribute directly to the technologies we’re building and to the computing capacity they can make possible.

About the Role

We are seeking an experienced and visionary Director, Physical Design to spearhead full-chip and complex subsystem physical design activities for Kepler's next-generation UHBM-based 3D-memory AI accelerator platform. This is a high-impact, high-visibility technical leadership role working closely with UnCore and Core architecture, RTL design, DFT, packaging, and foundry teams responsible for driving the physical design team from netlist ingestion through GDSII signoff. The ideal candidate will combine deep technical expertise in full-chip physical design with strong cross-functional leadership serving as the primary technical authority for physical design methodology, flow development, and execution, bringing the ability to make well-reasoned VLSI trade-off decisions across PPA, schedule, and design quality in a fast-paced startup environment.

Responsibilities:

Technical Leadership & Strategy

• Work with SoC architecture and Chip Lead teams to generate and analyze data supporting floorplan aware micro-architecture decisions from a physical design perspective.

• Assess and evaluate IP and technology options - work with SoC team, IP vendors, and design service partners to evaluate physical design floorplan feasibility, area, and power implications of IP and process node.

• Drive Design Service partner - evaluate and work with external Design Service partner for netlist through GDS implementation. Evaluate and ensure best PPA metric methodology, tools and implementation.

• Lead and drive the full-chip and multi-block physical design - from netlist ingestion through floorplanning, placement, CTS, routing and GDSII signoff, ensuring closure on PPA goals across all design blocks.

• Drive critical path closure - make architectural and implementation decisions to resolve complex timing, congestion, power-aware design and DRC challenges at advanced technology nodes.

Design Execution

1. Drive full-chip physical implementation - using Cadence Innovus Implementation System as the primary PD tool; leverage Cadence Genus iSpatial / Innovus integrated flow; hands-on experience with Synopsys IC Compiler II (ICC2) and/or Fusion Compiler is a plus.

2. Own implementation convergence - drive physical design execution through floorplanning, placement, CTS, routing, ECO and signoff in close coordination with synthesis, STA, DFT, and verification teams; ensure adherence to LINT, CDC and LEC quality standards.

3. Develop and own floorplanning strategies for large SoC designs — including partition planning, macro placement, pin assignment, power domain definition and TSV placement planning for the UHBM 3D-memory stack.

4. Manage power integrity - develop and review power grid strategies for the compute die and 3D-memory interface; perform IR drop and electromigration (EM) analysis using Cadence Voltus or ANSYS RedHawk; account for TSV-based power delivery constraints unique to the UHBM architecture.

5. Drive CTS strategy - implement and optimize clock tree synthesis for complex multi-clock, multi-voltage domain designs using mesh, spine, H-tree and shielded clock routing methodologies; leverage CCOPT (Concurrent Clock and Data Optimization) for multi-corner CTS closure.

6. Coordinate STA signoff - work closely with the timing team on timing-driven placement, congestion-aware routing and SI-aware signoff; review critical path timing reports and drive PD-driven ECO fixes.

7. Drive physical verification - own DRC/LVS/ERC signoff using Mentor Calibre or IC Validator; drive clean tapeout across all design blocks.

8. Drive signal integrity (SI) closure - analyze and resolve crosstalk delta-delay, glitch, and noise margin violations across critical interfaces including the TSV-based DRAM interface.

3D-IC Hard IP development

• Drive physical design for the 3D-memory PHY - develop and implement PD strategies for distributed TSV-based die-to-DRAM connectivity; align TSV placement, keep-out zones, and routing constraints with packaging and memory controller teams.

• Interface with packaging and foundry teams - drive physical design decisions related to 2.5D/3D-IC integration, interposer design, chiplet connectivity (UCIe, BoW), bump/micro-bump assignment and die-to-die interface constraints.

• Navigate 3D foundry design rules - implement 3D-specific design rules and routing constraints from foundry partners.

• Support IP hardening and delivery - experience with delivering hard IP (GDSII, timing models, LEF/DEF) to internal and external customers.

DFT & Low-Power Physical Implementation

• Drive DFT-aware physical design - implement scan chain routing, BIST controller placement, JTAG and boundary scan cell integration and test-mode power domain constraints in close coordination with the DFT Lead team.

• Implement low-power design strategies - UPF-based multi-voltage domain implementation, power gating, retention flop placement, level shifter and isolation cell insertion and low-power CTS strategies.

Cross-Functional Collaboration

• Drive all aspects of physical design in close partnership with UnCore/Core Design, DFX, Synthesis, STA, Design Service, Foundry and Packaging teams.

• Work collaboratively with the post-silicon validation team - ensure physical design decisions support efficient silicon bring-up, functional validation, electrical characterization and debug.

Team Leadership & Management

• Lead and drive a team of physical design engineers across Design Service partners and a small internal team for hard IP blocks; foster a culture of technical ownership, rigor and continuous improvement.

• Drive team planning and execution - resource allocation, task prioritization, schedule management and milestone tracking; report to program management.

• Ensure regular and high-quality reviews, checks, and sign-offs - conduct floorplan reviews, CTS reviews, timing closure reviews and tapeout readiness reviews.

• Participate in strategic product discussions - contribute to product feature definition and EDA tool decisions.

• Drive tapeout readiness - own final GDS signoff checklist, tapeout readiness reviews and foundry handoff.

Requirements:

• B.E. / B.Tech / M.Tech / MS in Electronics, Electrical Engineering, VLSI, or related discipline.

• 15–20 years of progressive, hands-on experience in ASIC/SoC Physical Design with a strong track record of silicon-proven tapeouts and successful productizations.

• Expert-level proficiency in Cadence Innovus Implementation System as the primary PD tool; experience with Cadence Genus iSpatial / Innovus integrated flow strongly preferred.

• Deep expertise in advanced node physical design in 7nm, 5nm, 3nm, including FinFET-specific design rules and routing challenges.

• Strong understanding of CTS methodologies - mesh, spine, H-tree, shielded clock routing, multi-corner CTS and CCOPT-based concurrent clock and data optimization.

• Proficiency in timing-driven placement, congestion-aware routing and SI-aware signoff.

• Prior experience with IP hardening and delivery - GDSII, timing models and LEF/DEF deliverables to internal or external customers.

• Solid knowledge of SoC implementation flows and physical verification - DRC/LVS/ERC signoff using Mentor Calibre or IC Validator; interaction with synthesis (Genus/DC), SDC constraints and STA signoff.

• Experience with NoC/Fabric/AXI interconnect physical implementation - placement and routing of high-performance on-chip networks.

• Experience with DFT-aware physical design - scan chain routing, BIST controller placement, JTAG/boundary scan integration and test-mode physical constraints.

• Experience with low-power physical implementation - UPF-based multi-voltage domains, power gating, retention flop placement, level shifters and isolation cells.

• Excellent leadership, communication and stakeholder management skills; proven ability to drive complex PD programs in a fast-paced environment.

• Proven track record of multiple successful SoC productizations - from physical design through post-silicon qualification and production release.

Nice to Have:

• Exposure to 3D-IC, chiplet, or advanced packaging design flows - HBM base die physical design, EMIB, UCIe, or similar die-to-die interface physical implementation; experience with TSV-based physical design constraints is a strong differentiator for this role.

• DDR PHY physical design experience - implementation of DDR4/DDR5/LPDDR4/LPDDR5 or HBM PHY blocks; understanding of analog/mixed-signal co-existence and PHY-specific timing/SI challenges.

• Strong scripting and automation skills - Tcl (Innovus scripting), Python, Perl for flow development, custom analysis and PD automation.

• Prior startup experience - demonstrated ability to deliver high-quality physical design results with lean teams, aggressive timelines and rapidly evolving product requirements.

Compensation and Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, paid time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [email protected].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.